An Introduction to OpenPiton
a Manycore Open Source Processor

Sunday, June 19th 2016, 9 AM, Seoul, Korea

OpenPiton is an open source framework designed to enable scalable architecture research prototypes from 1 core to 500 million cores. OpenPiton is the world’s first open source, general-purpose, multithreaded manycore processor and framework. OpenPiton leverages the industry hardened OpenSPARC T1 core with modifications and builds upon it with a scratch-built, scalable uncore creating a flexible, modern manycore design. In addition, OpenPiton provides synthesis and backend scripts for ASIC and FPGA to enable other researchers to bring their designs to implementation. On FPGA, OpenPiton provides a new high performance memory controller. OpenPiton provides a complete verification infrastructure of over 8000 tests, is supported by mature software tools, runs full-stack multiuser Debian Linux, and is written in industry standard Verilog. Multiple implementations of OpenPiton have been created including a taped-out 25-core implementation in IBM’s 32nm process and multiple Xilinx FPGA prototypes.

This tutorial will introduce the user to OpenPiton including how to use the framework to build different designs. The tutorial will introduce the verification framework (Verilog simulation), how to synthesize an OpenPiton processor for a Xilinx FPGA board, it will demonstrate booting Linux on an FPGA version of OpenPiton, it will familiarize users with how to use the OpenPiton framework to target an ASIC tapeout, and it will show users how to configure and extend the OpenPiton architecture to enable architecture research.

Researchers in academia or industry looking for a free, open-source, manycore hardware platform. Applicable uses include computer architecture research, EDA-tool exploration on a complex design, operating system research, and compiler research.

  1. Introduction
  2.      File Layout
  3.      Familiarization with what capabilities exist
  4.      Familiarization with documentation
  5. Simulation
  6.      How to simulate the RTL of OpenPiton
  7.      Introduction to 8000 test cases
  8.      How to add a test case
  9.      Familiarization with different test benches
  10.      Familiarization with test monitors
  11.      Hands-on writing a test case
  12. ASIC Synthesis and Backend
  13.      Familiarization with the OpenPiton ASIC flow
  14.      Synthesis
  15.      Place and Route
  16.      Timing Closure
  17.      Design Rule Checking
  18. FPGA
  19.      Overview of different boards supported
  20.      Overview of system-level hardware (I/O interfaces and memory interface)
  21.      Hands-on FPGA synthesis
  22.      Hands-on Booting Linux on OpenPiton on FPGA
  23. Configuration and Extension
  24.      Overview of configuration options
  25.      Hands-on configuring number of cores
  26.      Hands-on cache configuration
  27.      Discussion of different possible extensions and protocols
  28.           Interfacing to the NoC
  29.           Interfacing to the coherence protocol
  30. Operating System and System Software
  31.      Different available operating systems
  32.           Debian
  33.           Ubuntu
  34.      How to build Linux
  35.      Openboot Overview
  36.      Hypervisor Overview
  37. Q&A Session
  38. Closing Remarks

Attendees that wish to try out the hand-on tutorial should have a some experience with using Linux and a Linux-based text editor. Attendees should bring a laptop and charger for the tutorial. Each attendee will receive a USB flash drive containing: VirtualBox installers for Windows, Mac OS X, Linux; and a Linux virtual machine containing all of the code and tools for the tutorial, along with PDFs of the slides and handouts. Attendees will need approximately 15GB of free disk space to install and use the Virtual Box virtual machine.

  • David Wentzlaff
  • Michael McKeown
  • Jonathan Balkind

Linux booting on FPGA playing Tetris on OpenPiton
Tutorial Photo Gallery
OpenPiton Paper
Princeton Parallel Group


This work was partially supported by the NSF under Grants No. CCF-1217553, CCF-1453112, and CCF-1438980, AFOSR under Grant No. FA9550-14-1-0148, and DARPA under Grants No. N66001-14-1-4040 and HR0011-13-2-0005. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of our sponsors.